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AN1360 APPLICATION NOTE
Connecting the MPC56x Spanish OAK Microcontroller to the M58BW016B/D Flash Memory
CONTENTS
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INTRODUCTION This application note describes a method of connecting the M58BW016B/D Flash Memory to the Spanish OAK family of microcontrollers without using glue logic. The M58BW016B/D is an advanced 3V 16 Mbit flash memory from STMicroelectronics. It has a boot block architecture and includes a burst interface for high speed access. The M58BW016B has Tuning Block Protection (refer to Application note AN1361), whereas the M58BW016D has the Tuning Block Protection disabled. The MPC56x is a member of Motorola's Power-PC family of integrated microprocessors. It is a low voltage high performance 32-bit microcontroller designed for advanced automotive applications. It can run at a frequency of up to 56 MHz within the full automotive temperature range using a 2.6V power supply. The M58BW016B/D can operate at the 56 MHz maximum burst frequency required by MPC56x. The internal memory controller of the MPC56x supports single read/write operations, burst read operations, and provides a programmable and flexible bus interface. The main design consideration in connecting these two devices is the difference in the core power supplies. The electrical design flexibility of command lines, address and data bus of the MPC56x and the M58BW016B/D can be used to implement a full CMOS logic level interface. The method explained in this document can be used as a reference for other ST burst flash memories and other Power-PC microcontrollers (for example the MPC555). The different power supply levels and timings should be considered for each case.
INTRODUCTION POWER SUPPLY MANAGEMENT BUS ARCHITECTURE BUS OPERATIONS and TIMINGS CONCLUSION APPENDIX A. REGISTERS CONFIGURATION
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June 2001
Rev. 01A
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POWER SUPPLY MANAGEMENT The MPC56x is a low voltage microcontroller designed for advanced automotive applications. It's bus interface can operate at 56 MHz with a core supply of 2.6V (typ). The Input lines of the MPC56x are 3.3V tolerant. Please refer to the electrical specification for full description of the required power supplies, and power-up sequence (the MPC56x also requires a 5V supply). The M58BW016B/D is a x32 bus, 3V Flash Memory. An optional VPP of 12V can be provided to speed-up program and erase operations. Like other ST Flash memories, the M58BW016B/D has separate VDDQ, and VDDQIN power supply pins for I/O line buffers. This is useful to interface the Flash Memory device with lower or higher power supply devices. VDDQ(IN) can go from 2.4V to V DD (if VDD=3V, VDDQ can be between 2.4V and 3V). Figure 1. Power Supply Connections
VDD3 = 5V VDD1 = 2.6V VDD2 = 3.3V
M58BW016B/D VDDQ, VDDQIN ADDRESS BUS
Spanish OAK MPC565
DATA BUS I/O BUFFERS Flash Memory CORE
CONTROL BUS
HRESET
RP
VDD1 VDD2 RESET NETWORK
AI04504
Figure1 shows the recommended way to connect the power supplies. The VDD1 at 2.6V is used for the MPC56x core supply and the M58BW016B/D VDDQ supply. VDD2 at 3.3V (2.7V minimum) is mandatory to drive the core circuits of the Flash Memory. VDD3 (5 V) is provided for the MPC56x for its high voltage operations. Refer to the data sheets to check the minimum and maximum power supply ratings for each device. The two typical voltage levels (VDD1= 2.6V and VDD2= 3V) allow the devices to reach the maximum burst read frequency of 56 MHz. The bus high logic level is higher than 2.3V, so it is recognized as a CMOS high level by the input buffers of the two devices. The power consumption is at it's lowest in this situation. The two separate power supplies can be managed with a single chip multiple line supervisor circuit, to
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provide the appropriate reset signals to both devices. The reset pin on MPC56x (HRESET) is connected directly to the M58BW016B/D's RP pin. If the reset network detects a drop in VDD (on VDD1 or VDD2), both devices are automatically reset.
BUS ARCHITECTURE The MPC56x is normally configured as Big-Endian. The M58BW016B/D flash memory is Little-Endian, that is the hexadecimal data used to control the command interface uses D0 to equate to the Least Significant Bit. To interface the M58BW016B/D with the MPC56x without glue logic, the Address bus and the Data bus should be reversed; A29 on the MPC56x should be connected to A0 of the M58BW016B/D, A28 to A1, A27 to A2, etc.; D31 on the MPC56x should be connected to D0 on the M58BW016B/D, D30 to D1, D29 to D2, etc. See Table 1 and Figure 2. Table 1. Address, Data and Command Bus Connection
MPC56x M58BW016B/D Description The two least significant bits of MPC56x (A31 and A30) are not connected for a X32 word data transfer. A0 of the Flash memory corresponds to A29 of the MPC56x. The most significant bit of the memory, A18, is connected to A11 of the microcontroller. Data pins must be connected in the reverse order. Note: Flash Memory operations must be initialized with a data code (Tuning Protection code). If the scrambling between data lines is different, the command codes must be recalculated. Clock output of the microcontroller is the K input for the Flash Memory to synchronize the data transfer. One of the four Chip Select pins of MPC56x must be connected to the E pin of the flash. CS0 can be configured as global boot. Transfer start pin is used as Latch address enable (L for Flash Memory) every time a read or a write operation is performed by MPC56x. Read/Write pin for the MPC56x should be connected to the Write Enable pin of the Flash. The burst address advance pin is asserted low during a burst transfer when the next address locations are to be read during a burst sequence. The microcontroller drives it high when the address counter is not to be incremented. Output enable pin for both devices. Low when the Flash Memory is in read mode, High during a Flash write operation. The microcontroller forces a reset after a voltage drop on VDD supplies or a software reset. (the RP pin can also be connected to the SRESET pin of the MPC56x).
A29-A11
A0-A18
D0-D31
D31-D0
CLKOUT CSn TS RD/WR
K E L W
BDIP
B
OE
G
HRESET
RP
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Figure 2. Connecting the MPC56x to the M58BW016B/D
M58BW016B/D CLKOUT A29-A11 DQ31-DQ0 Spanish OAK MPC56x CSn TS RD/WR OE can control both flash B and G K A0-A18 DQ0-DQ31 I/O BUFFERS E L W B G Flash Memory CORE
{
(BDIP) OE
}
HRESET
RP
VDD1 VDD2 RESET NETWORK
AI04505
Note: OE can control both Flash BAA and G.
BUS OPERATIONS AND TIMINGS The signal timings of the two devices are compatible at the burst frequency of 56 MHz. During the boot access an asynchronous read is performed. After the reset command, an asynchronous read access is required from the flash memory. After the boot sequence, read and write operations or a burst read operation (the Burst Configuration Register must be configured first) can be performed. Figure 3 shows example timings for these operations. Refer to the data sheets of both devices for more details. The microcontroller default setting implies a 15 waiting states random access read. The SCY bits (number of wait states) of the MPC56x Memory Controller Option Register (ORx) must be set to 4 with a 56 MHz clock. In this way, the 4 wait states latency is used in the single cycle or in the first beat access of a burst read. During clock period 6 the data is sampled by the microcontroller strobe. After this delay sequence, the microcontroller strobe can detect the data valid on the rising edge of the last clock cycle. OE (G) signal is asserted low one clock cycle after the TS (L) and CSx (E) falling edge. In this case OE (flash) memory has the same timing as BDIP in normal assertion. A late BDIP can be also used (in this case flash OE can be connected to micro OE). Figure 4 shows a burst read at 56 MHz. The Burst Configuration Register of the M58BW016B/D (bits 13:11) is set to `1,0,0,2' in order to have 6 clock periods from the address latch to the first data beat. According to MPC56x ORx notation, the user must specify 4 extra wait states (SCY field) in the Memory Controller Option Register. The address latch clock period (1st) and data latch clock period (6th) are not considered to be wait states for the external memory interface of the MPC56x.The data beat can be held
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for just one clock period to perform a linear burst with a 1 period beat length (see Appendix A, Registers Configuration). These two settings (ORx and Flash Data Stream Register) define a 6-1-1-1 burst sequence. An example of a write cycle is provided in Figure 5. All write operations in both the MPC56x and the M58BW016B/D are asynchronous. After execution of the write cycles to initialize a program or erase operation in the flash memory, the result of that operation can be detected in the Status Register. Issue the Read Status Register command to output the contents of the Status Register. If the operation is still in progress a Read command will also output the contents of the Status Register. Refer to the M58BW016B/ D data sheet for more details on the Program, Erase and Read Status Register commands.
Figure 3. Single Read
tP,17.8ns (freq= 56MHz) CLKOUT (K) tLLKH, 6ns TS (L) tAVQV 80ns(max) CSx (E) tSTROBE,107ns A8-A29 (A18-A0) ADDRESS VALID 1 2 3 4 5 6
OE (G)
D0-D31 (D31- D0)
DATA VALID
RD/WR (W)
AI04506
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Figure 4. 56MHz 6-1-1-1 Burst Read
tP,17.8ns (56MHz) CLKOUT (K) 1 2 3 4 5 6
tLLKH,6ns TS (L) tAVQV,80ns(max) CSx (E)
A8-A29 (A18-A0)
ADDRESS VALID
OE (G) tQVKH,6ns D0-D31 (D31- D0) D1 VALID tKHQV,10ns D2 VALID D3 VALID D4 VALID
BDIP (B)
LATE OR NORMAL BDIP
RD/WR (W)
AI04507
Figure 5. Write Cycle at 56 MHz
tP, 18ns CLKOUT (K) 1 2 3 4 5 6
TS (L)
CSx (E) tAVLH, 12ns A8-A29 (A18-A0) ADDRESS VALID
OE (G)
D0-D31 (D31- D0)
DATA VALID tDVWH, 75ns
RD/WR (W)
AI04508
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APPENDIX A. REGISTERS CONFIGURATION Table 2. M58BW016B/D: Burst Configuration Register
Bit M15 M14 001 010 M13-M11 X-Latency (2) 011 100 101 110 M10 M9 Y-Latency (3) 0 1 0 M8 Valid Data Ready 1 0 M7 Burst Type 1 0 M6 M5-M4 0 M3 Wrapping 1 001 M2-M0 Burst Length 010 111 No wrap 4 Double-Words 8 Double-Words Continuous Valid Clock Edge 1 Rising Burst Clock edge Reserved Wrap Sequential Falling Burst Clock edge R valid Low one data cycle before valid Burst Clock edge Interleaved Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved Reserved 4, 4-1-1-1 (1) 5, 5-1-1-1, 5-2-2-2 6, 6-1-1-1, 6-2-2-2 7, 7-1-1-1, 7-2-2-2 8, 8-1-1-1, 8-2-2-2 Reserved One Burst Clock cycle Two Burst Clock cycles R valid Low during valid Burst Clock edge Value Synchronous Burst Read Description
Note: The 16 bit Burst Configuration Register is used to configure the read access of the Flash Memory.
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Table 3. MPC56x: External Memory Base Register (BRx)(1) Configuration
Bit 0-16 17-19 20-21 22 23 24-26 27 28 29 30 31 Name Base Address Address Type Port Size Reserved Write Protect Reserved TBDIP LBDIP SETA Burst Inhibit Valid Value User defined User defined 00 0 User Defined 000 0 0 0 User Defined 1 No toggle BDIP No late BDIP No external TA 0 = Enable Burst Access (instruction fetch only) 1 = Disable Burst Access To activate the current Bank 0 = Flash can be programmed 1 = Flash Memory Read Only Description The Flash Memory base address The user assigns the flash to any address space. 32 bit port size
Note: 1. "x" is the number of the chip select assigned to the Flash Memory address space.
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Table 4. MPC56x: External Memory Option Register (ORx)(1) Configuration
Bit 0-15 16 17-19 20 21-22 23 24-26 28-30 31 Name Address Mask Address Mask bit 16 Address Type Mask CSNT ACS EHTR SCY BSCY TRLX Value User defined 0 User defined 0 00 0 100 0 0 Description 0xffe0 for mask in 16 Mbit X32 bit setup Base Address mask bit 16 is always turned on for all setups More than one address space type can be assigned to a chip select. Chip select negation time No delay needed Extended hold time not needed 4 wait states + 2 = 6 clocks for first access or burst initial latency. Same wait states used for the write cycle. 0 wait states clock per data beat No TRLX needed
Note: 1. "x" is the number of the chip select assigned to Flash Memory address space.
CONCLUSION The M58BW016B/D can be connected to the MPC56x in a glue-less configuration, providing burst performance at 56MHz in the full automotive temperature range (-40 to 125C).
REVISION HISTORY
Date 05-Jun- 2001 Version -01 First Issue Revision Details
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If you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address:
ask.memory@st.com
(for general enquiries)
Please remember to include your name, company, location, telephone number and fax number.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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